1. Field of the Invention
This invention relates to manipulating, storing and testing data in electronic data processing systems, and more particularly, relates to manipulating, storing and testing data in character format in word-oriented processing systems.
2. Description of the Prior Art
In the past, character oriented processors have manipulated data in character format. An example is the 68020 Motorola microprocessor which uses index auto-incrementation to step from one byte to an adjacent byte. An instruction which uses an address and points to a byte in memory is automatically incremented to the next byte for the next memory reference. While this system operates well with a byte-oriented system, this approach does not apply to a word-oriented processor.
In word-oriented processors, an entire word is typically read from memory, and the appropriate byte is selected therefrom. Thus, the addressing of a particular byte typically includes a word address and a byte address. Because a character string may cross a word boundary, the process of reading a string of characters from a memory can be more complex than in the byte-oriented processors.
Character string manipulation is a common operation in many of today's computer applications. Many string operations involve identifying or comparing characters within a string. This often involves comparing each character in a string to a known value, such as a null or zero value. In many word oriented processors, this is accomplished by sequentially loading each character into an arithmetic register, and then comparing the loaded character to a desired value. In most systems, the characters must also be right justified before the compare to properly align the corresponding bits. Thus, at least two instructions are typically required to compare each character of a string with a desired value. This can consume a considerable amount of computation time.
To improved the speed and efficiency of byte access instructions in a word oriented data processing system, a load string (LS) and store string (SS) instruction have previously been developed. The load string and store string instructions utilize an indexed addressing scheme that includes a bank address field, a word offset field and a bite offset field. The word offset field is typically added to the bank address field to identify a particular word within the addressed memory bank. The bit offset field is used to identify a particular byte within the addressed word. Often, a character length field is also provided for identifying the bit width of each character in the string.
Using this addressing scheme, the Load String and Store String instructions may auto-increment the address after each load, such that the next character in a string is automatically referenced, without having to use the arithmetic logic unit (ALU) of a processor. This is accomplished by providing dedicated hardware separate from the ALU of the processor for incrementing the bit offset field by the character width. If the bit offset field is incremented past a word boundary, the word offset field is incremented by one, and the bit offset field is adjusted by subtracting the word length. As indicated above, this index manipulation may occur automatically in the hardware.
While the LS and SS instructions greatly improve the performance of loading and storing characters within a word oriented processor, the often used task of loading and comparing characters to a desired value may still require two separate instructions; namely the load instruction (LS) and a character compare instruction. Thus, at least two instruction cycles are typically required for each character compare.
It would be desirable, therefore, to provide a single instruction that can load a character from memory, and perform a compare. This may significantly increase the performance of many string operations, and in particular, those string operations that identify a particular character or combination of characters.